Empirical failure analysis and validation of fault models in CMOS VLSI

A methodology for the experimental evaluation of fault models, using fault diagnosis as the basic approach, is developed. The methodology includes a way of determining the defect level of test sets, in addition to determining the adequacy of the fault models used to generate them. The key elements of the method are the design and fabrication of an easily diagnosable test chip, representative of the class of circuits being studied, the CAD (computer-aided-design) tools used in its design, and its fabrication process; the derivation of an extremely robust test set, capable of detecting faults from within a wide range of fault models; the development of a set of diagnostic tools to perform automated diagnosis on faulty circuits and the use of the results to get measures of `effectiveness´ of the fault models considered; the validation of the results of the diagnosis by means of an electron-beam voltage-contrast circuit prober. Experimental results from a large number of samples of the test circuit are presented