On the evaluation of process-fault tolerance ability of CMOS integrated circuits

Author

Sicard, Etienne ; Kinoshita, Kozo

Author_Institution

Dept. of Appl. Phys., Osaka Univ., Japan

fYear

1990

fDate

10-14 Sep 1990

Firstpage

948

Lastpage

954

Abstract

Some algorithms and applications of inductive fault analysis (IFA) for the design of process-induced fault-tolerant VLSI CMOS circuits are presented. Starting from a mask-level IC design, the IFA procedure extracts all circuit-level faults which may result in the induction of a parasitic physical defect owing to an impure process fabrication. Algorithms concerning the fault list extraction, the density-fault map, and layout-to-schematic tools are detailed and illustrated through comprehensive examples. Applications of IFA cover validation of fault models, better fault coverage of test pattern sets, optimization of process fault-tolerant designs, and evaluation of the effectiveness of new design strategies

Keywords

CMOS integrated circuits; VLSI; circuit analysis computing; failure analysis; fault location; integrated circuit testing; integrated logic circuits; logic testing; optimisation; CMOS integrated circuits; VLSI; circuit-level faults; density-fault map; fault coverage; fault list extraction; impure process fabrication; inductive fault analysis; layout-to-schematic tools; mask-level IC design; optimization; parasitic physical defect; process-fault tolerance ability; validation; Algorithm design and analysis; CMOS integrated circuits; CMOS process; CMOS technology; Circuit faults; Fabrication; Physics; Probability; Process design; Statistical distributions;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114115

Filename

114115