Title :
A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier
Author :
Sinangil, Mahmut E. ; Verma, Naveen ; Chandrakasan, Anantha P.
Author_Institution :
Massachusetts Inst. of Technol., Cambridge, MA, USA
Abstract :
8 T bit-cells hold great promise for overcoming device variability in deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8 T test array fabricated in 45 nm CMOS achieves functionality from 1.1 V to below 0.5 V. Test chip operates at 450 MHz at 1.1 V and 5.8 MHz at 0.5 V while consuming 12.9 mW and 46 ¿W respectively.
Keywords :
CMOS integrated circuits; SRAM chips; nanoelectronics; 8T column-interleaved SRAM; CMOS; column circuitry; on-chip reference selection loop; power 12.9 mW to 46 muW; pseudodifferential scheme; reference selection loop; sense-amplifier sharing; size 45 nm; soft-error immunity; test chip; voltage 1.1 V to 0.5 V; Analytical models; Capacitance; Circuit testing; Delay; Error correction codes; Low voltage; Random access memory; Solid state circuits; Stability; Transient analysis;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357219
