Circuits for on-chip learning in neuro-fuzzy controllers

Learning algorithms have become of great interest to be applied not only to neural or hybrid neuro-fuzzy systems, but also as a tool to achieve a fine tuning of analog circuits, whose main drawback is their lack of precision. This paper presents accurate, discrete-time CMOS building blocks to implement learning rules on-chip. Specifically, a voltage mode high precision comparator as well as an absolute value circuit. These blocks, plus multiplexing in time techniques, are used to build a circuit to determine the polarity of the learning increments. Compactness and low power consumption have been considered the main requirements, since they are essential to increase the complexity of the neural systems. An example circuit has been simulated with HSPICE with the parameters of a 1 μm CMOS technology. Statistical variations of technological parameters were considered. The results show that all curves from 30 runs of a Monte Carlo analysis behave as expected, and at least 8 bits of resolution is achieved by the proposed techniques