Title :
Vertical tree 3-dimensional TSV clock distribution network in 3D IC
Author :
Kim, Dayoung ; Kim, Joohee ; Pak, Junso ; Lee, Hyungdong ; Lee, Junho ; Park, Kunwoo ; Kim, Joungho
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
fDate :
May 29 2012-June 1 2012
Abstract :
As through silicon via (TSV) technology is in the spotlight as the vertical interconnection method for 3-dimensional integrated circuit (3D IC), the study about a new structure of the 3-dimensional TSV clock distribution network (3D CDN) is strongly needed. In this paper, we propose a new 3D CDN scheme, vertical tree 3D CDN (VT 3D CDN), to reduce the skew, and we analyze the performances which is the skew, the jitter, the power consumption and the area consumption. The proposed VT 3D CDN improves the performance of the skew, although the other performance is slightly degraded.
Keywords :
clock distribution networks; integrated circuit interconnections; jitter; three-dimensional integrated circuits; 3-dimensional integrated circuit; 3D IC; area consumption; jitter; power consumption; skew reduction; through silicon via technology; vertical interconnection method; vertical tree 3-dimensional TSV clock distribution network; Clocks; Integrated circuit interconnections; Jitter; Power demand; Random access memory; Through-silicon vias;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6249105
