DocumentCode :
2727636
Title :
SoC memory optimization using loop transformations
Author :
Bouchebaba, Y. ; Gagné, V. ; Nicolescu, G. ; Aboulhamid, M.
Author_Institution :
Ecole Polytechnique de Montreal, Que.
fYear :
2006
fDate :
38869
Firstpage :
189
Lastpage :
192
Abstract :
In today´s embedded systems, the memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia applications using temporary multi-dimensional arrays that are typically used to store intermediate results during multimedia processing. In this paper, we introduce a new buffer allocation method to replace these temporary arrays and we combine it with loop fusion and tiling. The simple and effective method we present simultaneously applies tiling with fusion to a set of loop nests. Then, it replaces temporary arrays with smaller buffers containing the useful data. These new techniques allow to optimize memory space and reduce the number of cache misses. Our buffer allocation method is implemented in the PIPS compiler and the experiments are made on the StepNP simulator. They show that our technique yields a significant reduction in the number of data cache misses (on average, the data cache miss ratio is decreased by 14.3%)
Keywords :
cache storage; embedded systems; multimedia systems; program compilers; system-on-chip; PIPS compiler; SoC; StepNP simulator; buffer allocation method; data cache; embedded systems; loop transformations; memory optimization; multimedia processing; Buffer storage; Costs; Embedded system; Hardware; Multimedia systems; Power dissipation; Scanning probe microscopy; Streaming media; Tiles; Video sequences;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006 IEEE North-East Workshop on
Conference_Location :
Gatineau, Que.
Print_ISBN :
1-4244-0416-9
Electronic_ISBN :
1-4244-0417-7
Type :
conf
DOI :
10.1109/NEWCAS.2006.250903
Filename :
4016934
Link To Document :
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