Title :
Low Dead Time, Multi-hit FPGA-Based Time-to-Digital Converter
Author :
Amiri, Amir Mohammad ; Boukadoum, Mounir ; Khouas, Abdelhakim
Author_Institution :
Ecole Polytechnique Montreal, Que.
Abstract :
This paper presents improvements on a novel FPGA-based multi-hit time-to-digital converter (TDC) to measure time intervals with a resolution of 100ps and a variable dynamic range controlled by a binary coarse counter. We use a matrix topology to provide a two-level resolution, aiming to minimize the overall measurement time. The conventional dead time is eliminated by the continuous detection and processing of data by two delay matrices operating in parallel. A back-resetting scheme eliminates the erroneous multi-detection of an event along matrix tap lines. The circuit was tested on a XILINX SPARTAN-3 FPGA platform
Keywords :
field programmable gate arrays; integrated circuit design; logic design; FPGA; binary coarse counter; delay matrices; matrix topology; time-to-digital converter; Circuit testing; Circuit topology; Clocks; Counting circuits; Delay effects; Delay lines; Interpolation; Latches; Signal resolution; Time measurement;
Conference_Titel :
Circuits and Systems, 2006 IEEE North-East Workshop on
Conference_Location :
Gatineau, Que.
Print_ISBN :
1-4244-0416-9
Electronic_ISBN :
1-4244-0417-7
DOI :
10.1109/NEWCAS.2006.250905
