TSV stress testing and modeling

3D interconnect technology bonds semiconductor wafers and dies to produce multilevel chips with an optimum combination of cost, functionality, performance, and power consumption. This technology provides a pathway toward integrating CMOS ICs, as well as CMOS chips with emerging technologies. One major challenge of 3D IC integration is the reliability due to thermal stress during the process. The investigation on the stress measurement and analysis of through-silicon vias (TSVs) is important for 3D IC development. This work will summarize the measurement setup and finite element method (FEM) modeling results to investigate the stress profiles and processing effects for TSVs based on the use of a Piezo stress sensor embedded in a test element group (TEG) and a digital image analyzer (DIA). The results can be used to develop guidelines for the TSV density and pitch affecting Si damage.