A 29mm/sup 2/ 1.8 V-only 16 Mb DINOR flash memory with gate-protected poly-diode (GPPD) charge pump

Author

Mihara, Mitsuharu ; Miyawaki, Y. ; Ishizaki, O. ; Hayasaka, Takeshi ; Kobayashi, Kaoru ; Omae, T. ; Kimura, Hiromitsu ; Shimizu, Shogo ; Makimoto, H. ; Kawajiri, Y. ; Wada, N. ; Sonoyama, H. ; Etoh, J.

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

fYear

1999

fDate

17-17 Feb. 1999

Firstpage

114

Lastpage

115

Abstract

1.8 V-only 16 Mb CMOS divided-bit line-NOR (DINOR) flash memory with alternating background-operation (BGO) capability has 72 ns random access time. The EGO feature allows program or erase in one bank while the device simultaneously allows read in the other bank. This BGO feature is suitable for mobile and personal computing, and communication products. This memory is fabricated using a 0.25 /spl mu/m-design-rule, triple-layer-metal, triplewell CMOS. The cell is 0.80/spl times/0.85 /spl mu/m/sup 2/ and the chip is 4.93/spl times/5.88 mm/sup 2/.

Keywords

CMOS memory circuits; NOR circuits; flash memories; mobile computing; 0.25 micron; 1.8 V; 16 Mbit; 72 ns; DINOR flash memory; alternating background-operation capability; charge pump; divided-bit line-NOR; gate-protected poly-diode; mobile computing; personal computing; random access time; triple-layer-metal technology; triplewell CMOS; CMOS integrated circuits; CMOS memory circuits; Charge pumps; Diodes; Electrodes; Flash memory; MOSFETs; Nonvolatile memory; P-n junctions; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-5126-6

Type

conf

DOI

10.1109/ISSCC.1999.759158

Filename

759158