DocumentCode
2728683
Title
Improve transition fault diagnosability via observation point insertion
Author
Cheng-Hung Wu ; Yi-Da Wang ; Kuen-Jong Lee
Author_Institution
Dept. EE, Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2015
fDate
27-29 April 2015
Firstpage
1
Lastpage
4
Abstract
In this work, a design for diagnosability (DFD) method based on observation point (OP) insertion is proposed to improve the diagnosis resolution of transition faults in a circuit. The main objective is to minimize the number of observation points since this number will directly affect the area overhead of the circuit. We develop a novel algorithm to generate a set of OP candidates and then select a minimal number of OPs from this set which can distinguish all targeted fault pairs. An observation point insertion logic is also proposed that can efficiently reuse the output pins in the original circuit so as to reduce the number of extra output pins. In addition, a novel structural distance calculation method for synthesized circuits is proposed that considers the mixed structure of primitive gates and complicated gates, including AOI or OAI gates. Experimental results show that after applying the OP insertion method, all aborted fault pairs can be distinguished and the number of required observation points is quite small. We also use the observation points to distinguish those indistinguished far-away fault pairs. Experimental results show that all targeted fault pairs can be distinguished with a few observation points and a set of diagnosis patterns for ISCAS89 and ITC99 circuits.
Keywords
design for testability; fault diagnosis; logic design; ISCAS89 circuits; ITC99 circuits; design for diagnosability method; observation point insertion logic; structural distance calculation method; transition fault diagnosability; Algorithm design and analysis; Automatic test pattern generation; Circuit faults; Fault diagnosis; Logic gates; Multiplexing; Pins; Fault diagnosis; bridging faults; distinguishing multiple types of faults; stuck-at-faults;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location
Hsinchu
Type
conf
DOI
10.1109/VLSI-DAT.2015.7114571
Filename
7114571
Link To Document