Title :
Purely Digital BIST for Any PLL or DLL
Author :
Sunter, Stephen ; Roy, Aubin
Author_Institution :
LogicVision Inc., San Jose, CA
Abstract :
PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure <10 ps RMS jitter or >1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, output frequency, duty cycle, and other parameters. Its multi-GHz range, sub-picosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.
Keywords :
built-in self test; delay lock loops; discrete Fourier transforms; integrated circuit testing; jitter; phase locked loops; sampling methods; DLL; FPGA; PLL; SerDes; built-in self-test; delay lock loop; digital BIST; phase-locked loops; sub-picosecond jitter noise floor; undersampling; Built-in self-test; Calibration; Circuit noise; Circuit testing; Field programmable gate arrays; Frequency; Heart; Jitter; Phase locked loops; Silicon;
Conference_Titel :
Test Symposium, 2007. ETS '07. 12th IEEE European
Conference_Location :
Freiburg
Print_ISBN :
0-7695-2827-9
DOI :
10.1109/ETS.2007.35
