A Feature-Based Optical Flow Processor Architecture Featuring Single-Motion-Vector/Cycle Generation

A feature-based optical flow processor architecture has been developed. It has a special data allocation scheme in on-chip SRAM banks and a parallel shift and matching unit using compact absolute difference circuits. As a result, single-motion-vector/cyclc generation at arbitrary locations in the scene has been achieved. The core circuitries were designed in a 0.18-m 5-metal CMOS technology and sent to fabrication, and the operation was confirmed by Nanosim simulation. Although the simulation results arc limited to only the core circuitries, it is expected that the chip can generate optical flow about 10,000 times faster than software processing.