Performance characteristics of SOI DRAM for low-power application

Process integration of cell capacitors circumvents the difficulties of large topographic height difference and high temperature process. 16 Mb SOI DRAM with a 0.3 /spl mu/m design rules shows processing integrity and circuit performance based on process integration of the cell capacitor using the pattern-bonded SOI (PBSOI) technology. Measurements of RAS access time (tRAC) and operating current (Icc1) show >25% improvement for SOI DRAM compared to the 16 Mb bulk counterpart with the same circuit and layout. On the transistor side, ultra-low-voltage transistor technology using body bias control provides devices with small leakage current and almost ideal sub-threshold swing. The results give the guidance of transistor and process for low-power DRAM applications.