Low-impedance evaluation of power distribution network for decoupling capacitor embedded interposers of 3-D integrated LSI system

We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 40 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of 0.1 Ω could be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.