A low power implementation of a W-CDMA receiver on an ultra low power DSP

Author

Wang, Alice ; Hezar, Rahmi ; Gass, Wanda

Author_Institution

MIT, Cambridge, MA, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

241

Abstract

This paper present results from a wideband-CDMA downlink receiver implementation on the newly developed low-power Texas Instruments TMS320C55x DSP for wireless applications. The C55x includes new instructions and functional units, such as the dual multiply-accumulates (DualMAC), implicit/explicit parallelism, and an added pipeline stage. It also includes hardware in the address unit exclusively for memory address computation. This new architecture is suitable for implementation of systems that have large computational tasks and low-power requirements, such as baseband processing in the W-CDMA downlink receiver. The chip dissipates 0.25 mW/MIPS which is lower than the power dissipated in the current low power DSP, the C54x. We show that the C55x has a 40-60% improvement over the C54x in cycle efficiency in our implementation of a W-CDMA receiver

Keywords

broadband networks; code division multiple access; digital signal processing chips; land mobile radio; parallel architectures; radio links; radio receivers; DualMAC; Texas Instruments TMS320C55x DSP; W-CDMA receiver; address unit; baseband processing; cycle efficiency; dual multiply-accumulates; implicit/explicit parallelism; low power implementation; memory address computation; mobile communication services; pipeline stage; ultra low power DSP; wideband-CDMA downlink receiver; wireless applications; Baseband; Computer architecture; Digital signal processing; Digital signal processing chips; Downlink; Hardware; Instruments; Multiaccess communication; Parallel processing; Pipelines;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 2000. GLOBECOM '00. IEEE

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-6451-1

Type

conf

DOI

10.1109/GLOCOM.2000.892009

Filename

892009