DocumentCode :
2733144
Title :
GA Based Congestion Aware Topology Generation for Application Specific NoC
Author :
Choudhary, Naveen ; Gaur, M.S. ; Laxmi, V. ; Singh, Virendra
Author_Institution :
Dept. of Comput. Eng., Malaviya Nat. Inst. of Technol., Jaipur, India
fYear :
2011
fDate :
17-19 Jan. 2011
Firstpage :
93
Lastpage :
98
Abstract :
Network-on-chip (NoC) has been proposed as an alternate to wired communication frameworks of System-on-chip (SoC) design. Application specific SoC design requires custom NoC architectures, which may not be regular but are more suitable for a particular application. This paper presents a genetic algorithm for synthesis of custom NoC architectures for applications having IP cores with varying communication bandwidth requirements. The optimization objective of the technique is to improve communication load and energy distributions across the network subject to the resource constraints in such a way that the overall efficiency in terms of throughput and communication latency improves. Experimental results show that customized irregular NoC clearly outperforms the traditional regular mesh architecture in terms performance.
Keywords :
genetic algorithms; integrated circuit design; network synthesis; network topology; network-on-chip; GA-based congestion aware topology generation; IP cores; NoC architecture synthesis; SoC design; application specific NoC; communication bandwidth requirements; communication latency; communication load; energy distributions; genetic algorithm; mesh architecture; network-on-chip; system-on-chip design; wired communication frameworks; Core Graph; Genetic Algorithm; Irregular NoC; Optimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium on
Conference_Location :
Queenstown
Print_ISBN :
978-1-4244-9357-9
Type :
conf
DOI :
10.1109/DELTA.2011.26
Filename :
5729547
Link To Document :
بازگشت