CVD tungsten metallization and electron beam lithography for fabricating submicron interconnects for advanced ULSI

Author

Wilson, S.R. ; Mattox, R.J.

Author_Institution

Motorola, Mesa, AZ, USA

fYear

1988

fDate

13-14 June 1988

Firstpage

158

Lastpage

164

Abstract

CVD W (0.45- mu m-thick) and CVD W (0.25- mu m-thick) strapped by Al (0.5- mu m-thick) have been used as metal 1 systems. Electrical and physical data are presented from experiments exploring the effects of processing issued with both electron-beam and stepper lithography, as well as dry-etch chemistry on both metal systems. The special issues encountered with the thick tungsten processing were: (1) significant electron-beam proximity related problems as compared to the sandwich metal layers; and (2) multiple etch related problems due to mask failure and a lack of etch selectivity. A high-selectivity etch was developed that greatly reduced underlying dielectric damage and allowed the used of relatively thin organic and PEO (plasma-enhanced oxide) hardmask layers without mask failure.<>

Keywords

CVD coatings; VLSI; electron beam lithography; integrated circuit technology; metallisation; sputter etching; tungsten; CVD; W; W-Al; advanced ULSI; dielectric damage; dry-etch chemistry; electron beam lithography; electron-beam proximity; etch selectivity; mask failure; metallization; multiple etch related problems; plasma-enhanced oxide; stepper lithography; submicron interconnects; Artificial intelligence; Electron beams; Etching; Filling; Integrated circuit interconnections; Lithography; Metallization; Plasma chemistry; Resists; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE

Conference_Location

Santa Clara, CA, USA

Type

conf

DOI

10.1109/VMIC.1988.14188

Filename

14188