Multimodal Analysis of Stress Induced Degradation of 90nm Node Interconnects

On the basis of experiments reported in the literature and previously obtained results (Oshima et al., 2002), (Ogawa et al., 2002), (Jawarami et al., 1999) and (Fischer and Zitzelberger, 2001), we used structures having via connected to wide metal plates to enhance stress voiding failure. As a matter of fact, stress voiding phenomenon has been demonstrated to be vacancy diffusion limited. Therefore, the copper volume surrounding a via can be considered as a vacancy source. For this work, test structure consisted in single vias, wired in a 4 point arrangement to maximize resistance measurement accuracy. The vias tested are located between the first and second metal level. We optimized wiring to reach a high number of via per test structure and we reach a sampling of 900 vias per wafer