Performance analysis of reconfigurable SRAM cell for low power multimedia applications

High speed, low power SRAMs have become a critical component of many VLSI chips. This is especially true for microprocessors, where the on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and the main memory. Simultaneously, power dissipation has become an important consideration. A 64×64 SRAM memory system is designed, implemented and tested for correct read, write operation and performed the reconfiguration on memory system in order to optimize power. This paper presents a performance analysis of reconfigurable memory system for low power application. A 64×64 lena image is taken as test engine to validate the designed reconfigurable SRAM architecture. Simulations using TSMC 0.35um technology show that the SRAM cell read and write access times are 1.53ns and 1.93ns. Mentor Graphics ELDO and EZ-wave are used for simulations.