Delay optimized array multiplier for signal and image processing

The signal and image processing algorithm use multiplication as one of the basic arithmetic operation. So the efficient implementation of multiplier is always a challenge. The present work describes a method to build a faster array multiplier by delay optimized inter connection globally. The proposed array multiplier architecture performance in terms of delay and hardware is compared with conventional as well as recent reported one. This shows that for any length of multiplication the reported architecture is better than the conventional one. In terms of hard ware this architecture is also better than the last reported and gives less delay for length up to 12. But the reported one gives more delay for higher bit length multiplication. A detail analysis of all three architecture is give based on which a designer can decide to chose the specific array architecture for his multiplier as to requirement.