Title :
A test chip for CPAL register file fabricated in chartered 0.35μm CMOS process
Author :
Hu, Jianping ; Liu, Binbin ; Xuanyan Hu ; Zhang, Sheng
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo
Abstract :
A 32 times 32 register file based on complementary pass-transistor adiabatic logic (CPAL) has been fabricated with chartered 0.35 mum process. All the circuits except for the storage cells employ CPAL circuits. The storage cell is based on the conventional memory one. For comparison, a conventional 32 times 32 register file is also embedded in the chip. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show the CPAL register file can work very well, and it attains 57% energy saves than the conventions register file at 100 MHz.
Keywords :
CMOS logic circuits; logic design; low-power electronics; CPAL circuits; CPAL register file; chartered CMOS process; complementary pass-transistor adiabatic logic; energy simulation; frequency 100 MHz; functional simulation; size 0.35 mum; storage cells; test chip; CMOS logic circuits; CMOS process; CMOS technology; Capacitance; Energy loss; Logic circuits; Logic design; Logic testing; Registers; Voltage;
Conference_Titel :
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location :
Knoxville, TN
Print_ISBN :
978-1-4244-2166-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2008.4616829
