High performance CMOS driver-receiver pair using low-swing signaling for low power on-chip interconnects

This paper describes the design of a symmetric low-swing driver-receiver pair (mj-sib) for driving signals on the global interconnect lines. When implemented on 0.13 mum CMOS 1.2 V technology, mj-sib scheme reduces delay by up to 32% and energy-delay product by up to 45% (with a wire length of 10 mm and the extra fanout load of 2.5 pF on the wire) when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The key advantages of the proposed signaling scheme is that it requires only one power supply and threshold voltage, hence significantly reducing the design complexity.