A timing-driven synthesis approach of a fast four-stage hybrid adder in Sum-of-Products

In state-of-the-art integrated circuits, the arithmetic sum-of-products (SOP) is an important and computationally intensive unit, which tend to be in the timing-critical path of the design. Several arithmetic blocks like multipliers, multiply-accumulators (MAC), squarers etc. are special cases of the generalized sum-of-product block. The final carry propagate adder inside a sum-of-product block consumes about 30%-40% of the total delay of the SOP block and hence plays an important role in determining the performance of the overall design. In this paper, we present a novel approach to develop a fast implementation for the final adder block in a sum-of-product module. In our approach, we design a hybrid adder, which consists of four different sub-adders. The width of each of the sub-adders are computed based on the arrival times of the input signals to the hybrid adder. We have tested our approach using a variety of SOP blocks implemented under varying timing constraints and technology libraries. Experimental results demonstrate that our proposed solution is 14.31% faster than the corresponding block generated by a commercially available best-in-class datapath synthesis tool.