A 10 b 58 MHz CMOS A/D converter for high-speed video applications

Author

Jeon, Byeong-Lyeol ; Lee, Kang-Jin ; Lee, Seung-Hoon ; Yoon, Sang-Won

Author_Institution

Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea

fYear

1999

fDate

18-21 Jan 1999

Firstpage

29

Abstract

This paper describes a 10 b 50 MHz CMOS ADC for high-speed signal processing applications. The proposed pipelined ADC adopts a selective channel-length adjustment technique for current mismatch minimization, a power reduction technique for high-speed op amps, and a capacitor scaling technique for reduced power and chip area. The measured differential and integral nonlinearities of the prototype in a 0.8 μm CMOS show less than ±0.6 LSB and ±2.0 LSB, respectively. The typical power consumption is 119 mW at 3 V and 40 MHz, and 320 mW at 5 V and 50 MHz

Keywords

CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; pipeline processing; video signal processing; 0.8 micron; 10 bit; 119 to 320 mW; 3 to 5 V; 40 to 50 MHz; CMOS A/D converter; CMOS ADC; capacitor scaling technique; current mismatch minimization; high-speed op amps; high-speed signal processing; high-speed video applications; pipelined ADC; power reduction technique; selective channel-length adjustment technique; CMOS process; CMOS technology; Capacitors; Clocks; Energy consumption; High power amplifiers; Logic; Operational amplifiers; Prototypes; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.759702

Filename

759702