An Outside-Rail Opamp Design Targeting for Future Scaled Transistors

An outside-rail output opamp targeting for future scaled MOSFETs is designed and the 3-V-output operation is successfully verified using 1.8-V standard CMOS process. This is the first experimental verification of an outside-rail opamp design which shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-mum standard CMOS process. The chip area is estimated to be 47% of the conventional opamp using a 0.35-mum CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-mum CMOS design due to reduced capacitor area