An Integrated Functional Verification Tool for FPGA Systems

Author

Lee, Trong-Yen ; Fan, Yang-Hsin ; Yen, Shih-Chin ; Tsai, Chia-Chun ; Hsiao, Rong-Shue

Author_Institution

Nat. Taipei Univ. of Technol., Taipei

fYear

2007

fDate

5-7 Sept. 2007

Firstpage

203

Lastpage

203

Abstract

Hundreds of thousands circuits can not be verified easily while develop a field programmable gate array (FPGA) system. In this paper, we develop a functional verification tool, namely FVT, to verify the designer defined specification of functionalities with simulator and emulator in a FPGA system. In addition, FVT can point out the exact bugs for functionality where locates at specific cycle. Experiment results show that FVT can save time up to 99%.

Keywords

field programmable gate arrays; formal verification; emulator functionalities; field programmable gate array system; integrated functional verification tool; simulator functionalities; Circuit simulation; Computational modeling; Computer bugs; Costs; Fabrication; Field programmable gate arrays; Hardware; Prototypes; Signal detection; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovative Computing, Information and Control, 2007. ICICIC '07. Second International Conference on

Conference_Location

Kumamoto

Print_ISBN

0-7695-2882-1

Type

conf

DOI

10.1109/ICICIC.2007.155

Filename

4427848

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2736199