Threshold direct synthesis structure for digital delta-sigma modulators

In this paper, we propose an implementation for digital delta-sigma modulators named as threshold direct synthesis structure. The proposed configuration increases modulator throughput by decomposing a delta-sigma loop into two events, which can be completed in one input clock period. A third-order single-loop digital modulator is implemented using this method and an output/input rate ratio of 1:1 is obtained. Since a relatively low circuit speed is allowed, it can be used for a low power fractional-N frequency synthesizer implementation.