The implementations of adiabatic flip-flops and sequential circuits with power-gating schemes

The implementations of adiabatic flip-flops and sequential circuits are described in this paper. The flip-flops are realized with the two-phase CPAL (complementary pass-transistor adiabatic logic) circuits. The two-phase non-overlap power-clock generator is used to supply the CPAL sequential circuits, which is realized by using a simple converter and a single-phase sinusoidal power-clock. A power-gating scheme for the adiabatic sequential circuits is proposed. All circuits are implemented using Chartered 0.35 mum CMOS technology, and full-custom layouts are drawn. Based on the post-layout simulation results, the adiabatic sequential circuits with the power-gating scheme attain large energy savings over a wide range of frequencies, as compared with conventional CMOS circuits.