DocumentCode
2736310
Title
SRAM Circuit with Expanded Operating Margin and Reduced Stand-by Leakage Current Using Thin-BOX FD-SOI Transistors
Author
Yamaoka, Masanao ; Tsuchiya, Ryuta ; Kawahara, Takayuki
Author_Institution
Central Res. Lab., Hitachi, Ltd., Tokyo
fYear
2005
fDate
1-3 Nov. 2005
Firstpage
109
Lastpage
112
Abstract
We propose a low-power SRAM circuit using thin-BOX FD-SOI transistors. The SRAM circuit uses back-gate bias effectively, and acquires high operating margin and high speed operation under low supply voltage. The leakage current in standby state is reduced. This SRAM achieves 30% faster writing time under low-voltage operation, and 90% less stand-by power
Keywords
SRAM chips; leakage currents; low-power electronics; silicon-on-insulator; SRAM circuit; back-gate bias; stand-by leakage current; thin-BOX FD-SOI transistors; Circuits; Controllability; Energy consumption; Fluctuations; Laboratories; Leakage current; Low voltage; Random access memory; Transistors; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Solid-State Circuits Conference, 2005
Conference_Location
Hsinchu
Print_ISBN
0-7803-9162-4
Electronic_ISBN
0-7803-9163-2
Type
conf
DOI
10.1109/ASSCC.2005.251677
Filename
4017543
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