Implementation of an Efficient DWT Using a FPGA on a Real-time Platform

In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied by the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speeds up the clock rate of the DWT. The architecture is coded in Verilog HDI, implemented in a FPGA, and verified by the platform of Quartus-II which is a realtime platform comprising a CMOS image sensor, a FPGA and a TFT-ICD panel.