A Triple-Mode MAP/VA IP Design for Advanced Wireless Communication Systems

Author

Lin, Cheng-Hung ; Li, Fan-Min ; Shi, Xin-Yu ; Wu, An-Yeu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

fYear

2005

fDate

1-3 Nov. 2005

Firstpage

221

Lastpage

224

Abstract

In this paper, a triple-mode MAP/VA IP for advanced wireless communication Systems is implemented in 0.18mum CMOS process. We employ triple-mode MAP/VA timing charts that can run two different algorithms at the same time by complementing the idle time of each other. In order to conform to the advance communication standard, our IP can also perform as a reconfigurable trellis decoder. For WCDMA standard, this IP can operate at clock frequency of 100 MHz and achieve throughput rate of 4.17Mbps@6 iterations for turbo decoding and 1.56Mbps for convolutional decoding in concurrent MAP/VA mode from the worst-case static timing analysis and post-layout simulation

Keywords

3G mobile communication; CMOS integrated circuits; convolutional codes; 0.18 micron; 1.56 Mbit/s; 100 MHz; 4.17 Mbit/s; CMOS process; WCDMA standard; advanced wireless communication; convolutional decoding; post-layout simulation; reconfigurable trellis decoder; static timing analysis; triple-mode MAP/VA IP design; turbo decoding; Analytical models; CMOS process; Clocks; Communication standards; Frequency; Iterative decoding; Multiaccess communication; Throughput; Timing; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Solid-State Circuits Conference, 2005

Conference_Location

Hsinchu

Print_ISBN

0-7803-9162-4

Electronic_ISBN

0-7803-9163-2

Type

conf

DOI

10.1109/ASSCC.2005.251705

Filename

4017571