Title :
An 865-μW H.264/AVC Video Decoder for Mobile Applications
Author :
Liu, Tsu-Ming ; Lin, Ting-An ; Wang, Sheng-Zen ; Lee, Wen-Ping ; Hou, Kang-Cheng ; Yang, Jiun-Yan ; Lee, Chen-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
Abstract :
A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865-muW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4times4 sub-block level pipelining that achieves better buffer allocation and decoding throughput. In addition, several modules are designed with new features to improve overall system throughput (up to 260,000 macro-block/sec). The proposed solution integrates 456-k logic gates with 161Kb of embedded SRAM in 0.18-mum single-poly six-metal CMOS process with area of 11.3mm2
Keywords :
CMOS digital integrated circuits; mobile computing; video coding; 0.18 micron; 1.2 MHz; 1.8 V; 865 muW; CIF sequence format; H.264/AVC; HD sequence format; LSI; SD sequence format; mobile applications; quarter-common intermediate format; single-poly six-metal CMOS; sub-block level pipelining; video decoder; Automatic voltage control; CMOS logic circuits; Clocks; Decoding; Frequency; High definition video; Large scale integration; Logic gates; Pipeline processing; Throughput;
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9162-4
Electronic_ISBN :
0-7803-9163-2
DOI :
10.1109/ASSCC.2005.251725
