DocumentCode :
2737151
Title :
A 231MHz, 2.18mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3D Graphics System
Author :
Kim, Hyejung ; Nam, Byeong-Gyu ; Sohn, Ju-Ho ; Yoo, Hoi-Jun
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon
fYear :
2005
fDate :
Nov. 2005
Firstpage :
305
Lastpage :
308
Abstract :
A 32-bit fixed-point logarithmic arithmetic unit is designed for mobile 3D graphics system. The proposed logarithmic arithmetic unit performs division, reciprocal, square-root, reciprocal-square-root and square operations in 2-cycle, and powering operation in 5-cycle. It uses programmable precision for accurate 3D pipeline computation and 8-region piecewise linear approximation model for logarithmic and exponential conversion to reduce the operation error under 0.2%. Its test chip is implemented by 1-poly 6-metal 0.18mum CMOS technology with 9k gates. It operates at the maximum frequency of 231MHz and consumes 2.18mW
Keywords :
CMOS digital integrated circuits; computer graphics; coprocessors; fixed point arithmetic; mobile computing; 0.18 micron; 1-poly 6-metal CMOS; 2.18 mW; 231 MHz; 32 bit; 3D pipeline computation; exponential conversion; fixed-point 3D graphics system; logarithmic arithmetic unit; logarithmic conversion; mobile 3D graphics system; piecewise linear approximation; CMOS technology; Clocks; Computer graphics; Digital arithmetic; Energy consumption; Fixed-point arithmetic; Frequency; Laboratories; Pipelines; Real time systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9163-2
Electronic_ISBN :
0-7803-9163-2
Type :
conf
DOI :
10.1109/ASSCC.2005.251726
Filename :
4017592
Link To Document :
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