DocumentCode :
2738957
Title :
Fault-tolerant artificial neural networks
Author :
Kim, Jung H. ; Lursinsap, C. ; Park, Sung-Kwon
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
fYear :
1991
fDate :
8-14 Jul 1991
Abstract :
Summary form only given, as follows. Self-recovery methods in artificial neural networks (ANNs) implemented on a digital VLSI chip were investigated. Fault tolerance is the potential benefit of ANNs that extends beyond the high computation rates facilitated by the massive parallelism. If a faulty neuron or a faulty link occurs in ANNs implemented on a VLSI chip, typically ANNs no longer classify all inputs correctly. The ability of ANNs to achieve fault tolerance is not inherent, but must be built in. Also, the built-in fault-tolerant mechanism must be practical and efficient enough for a VLSI chip implementation. A partial relearning scheme was proposed to achieve fault tolerance. The scheme was applied to only a single neuron level, not entire networks. Therefore, the execution speed of the partial relearning will be much faster than that of the normal learning. Furthermore, the partial relearning can be executed in a parallel fashion
Keywords :
VLSI; fault tolerant computing; learning systems; neural nets; parallel architectures; ANNs; VLSI chip; artificial neural networks; computation rates; digital VLSI chip; execution speed; fault-tolerant mechanism; parallelism; partial relearning scheme; Artificial neural networks; Concurrent computing; Convergence; Fault tolerance; Neural networks; Neurons; Parallel processing; Power line communications; Space technology; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-0164-1
Type :
conf
DOI :
10.1109/IJCNN.1991.155560
Filename :
155560
Link To Document :
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