Title :
Modeling Reliability for Single-Electron Tunneling Logic Gates
Author :
Mao, Yanjie ; Chen, Chunhong
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON
Abstract :
This paper proposes a new reliability model for individual single-electron tunneling (SET) logic gates. We study a typical SET logic gate (2-input NAND gate) to quantitatively associate the gate reliability with actual process variations as well as input patterns. This model can be used in future CAD tools to analyze the reliability of SET-based digital logic circuits.
Keywords :
bifurcation; logic circuits; logic gates; nanoelectronics; reliability; single electron devices; CAD tools; NAND gate; SET logic gate; SET-based digital logic circuits; bifurcation analysis; nanoelectronic circuits; reliability model; single-electron tunneling; Capacitance; Circuit simulation; Digital circuits; Electrons; Fluctuations; Gaussian distribution; Logic circuits; Logic gates; Tunneling; Voltage;
Conference_Titel :
Nanotechnology, 2008. NANO '08. 8th IEEE Conference on
Conference_Location :
Arlington, TX
Print_ISBN :
978-1-4244-2103-9
Electronic_ISBN :
978-1-4244-2104-6
DOI :
10.1109/NANO.2008.117
