Back gate engineering for suppression of threshold voltage fluctuation in fully-depleted SOI MOSFETs

Threshold voltage fluctuation due to SOI thickness variation is one of the most serious problems in fully-depleted (FD) SOI MOSFETs. In order to suppress this threshold voltage (V_th) fluctuation in FD SOI-MOSFETs, we propose a new back gate engineering scenario in which the back gate is biased in order to make the back interface of SOI films weakly accumulated, under very thin buried oxides allowing strong coupling between back gate and Si films. It is shown theoretically and experimentally that this back gate engineering significantly reduces the V_th fluctuation, because of the balance between the amount of space charge in SOI films and the electric field at the front surface of the SOI films