Characterization of the parasitic bipolar transistor in SOI technology: comparison between direct and indirect triggering techniques

Soft error FIT (failure in time) requirements is an increasing challenge for high performance CMOS applications. Projections show that a 100 times increase in sensitivity is expected for the technologies produced in the next decade (Cohen et al, 1999). To reduce the sensitivity of ICs, different approaches have been tried such as the implementation of a circuit based solution to protect the memory arrays. However, these solutions are detrimental to the integration density and are impractical for protection of the random core logic. On the other hand, SOI technologies are a potential solution for reduction of the soft error rate. This is due to the buried oxide, which reduces the sensitive volume and suppresses deep charge collection by a funneling mechanism (Musseau, 1996). However, the parasitic bipolar junction transistor (p-BJT) inherent to the structure is a limiting factor that could be overcome by an effective solution as shown in previous studies (Ikeda et al, 1998). Thus, a better knowledge and investigation of this p-BJT is required to reduce or to suppress its effect in SOI devices. This work presents new results to improve the understanding of the mechanism that underlies the bipolar action