Title :
A scalable pipelined architecture for separable 2-D discrete wavelet transform
Author :
Jou, Jer Min ; Chen, Pei-Yin ; Shiau, Yeu-Horng ; Liang, Ming-Shiang
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
This paper presents a highly scalable efficient architecture for separable 2-D Discrete Wavelet Transform (DWT) which is simple, regular, modular and pipelined for the computation of 2-D DWT. With these properties, it is easily scalable for different filter lengths and different octave levels. In addition, the architecture has the characteristics of lower hardware cost, shorter latency, and higher throughput rate
Keywords :
VLSI; digital signal processing chips; discrete wavelet transforms; parallel architectures; pipeline arithmetic; VLSI architecture; different filter lengths; different octave levels; higher throughput rate; highly scalable efficient architecture; lower hardware cost; scalable pipelined architecture; separable 2-D discrete wavelet transform; shorter latency; Computer architecture; Costs; Delay; Discrete wavelet transforms; Filtering; Hardware; Image coding; Low pass filters; Throughput; Wavelet transforms;
Conference_Titel :
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location :
Wanchai
Print_ISBN :
0-7803-5012-X
DOI :
10.1109/ASPDAC.1999.759996
