Title :
A new global router for ASIC design based on simulated evolution
Author :
Chen, Yirng-An ; Lin, Youn-Long ; Hsu, Yu-Chin
Author_Institution :
Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan
Abstract :
A global router for gate array design is presented. The status of the routing area is represented as matrix. Rip-up and reroute operations are emulated as matrix operations. A rip-up and reroute global router, called TRACER, which is based on the simulated evolution technique, has been implemented using this representation scheme. Experimental results show that TRACER´s routing quality is better than that of all the other approaches
Keywords :
application specific integrated circuits; circuit layout CAD; logic CAD; logic arrays; ASIC design; TRACER; gate array design; global router; matrix operations; reroute operations; rip-up; routing area; routing quality; simulated evolution; Application specific integrated circuits; Channel capacity; Computational modeling; Computer science; Cost function; Logic circuits; Process design; Routing; Simulated annealing; Wires;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68626
