An SOI-based high performance self-aligned bipolar technology featuring 20 ps gate-delay and a 8.6 fj power-delay product.

Abstract This paper describes a high performance bipolar process based on bonded SOI wafers featuring deep trench isolation, double polysilicon self-alignment, and a substrate-erosion free composite spacer scheme. The process provides transistors with excellent dc and ac parameters. Gate delay times of 19.6 ps, power-delay products of 8.6 fJ, and 2:1 frequency dividers operating up to 22.4 GHz are prominent performance data which are - to the authors knowledge - best values ever reported for SOI-based bipolar technologies.