DocumentCode :
2747921
Title :
A comparative analysis of power and device utilization of LDPC and Turbo encoders
Author :
Qazi, Sohaib A. ; Kahkashan, Samra
Author_Institution :
CAST, COMSATS Inst. of IT, Islamabad, Pakistan
fYear :
2011
fDate :
23-24 July 2011
Firstpage :
1
Lastpage :
5
Abstract :
Today, the exponentially emergent requirements for high performance communication systems operating in noisy environments arise the need of high data rate with error free communication. Due to this reason, design of channel encoders becomes critical and a performance metric is required to qualify encoder for optimized solution. In this paper, we present two encoding techniques i.e. Low Density Parity Check (LDPC) and Turbo encoder. These techniques are evaluated on the basis of FPGA resource utilization and power consumption. Post PAR simulation results show that Low Density Parity Check encoder is more efficient in terms of through put, resource utilization and power consumption than Turbo encoder.
Keywords :
channel coding; field programmable gate arrays; parity check codes; turbo codes; FPGA resource utilization; LDPC; channel encoders; encoding techniques; error free communication; high performance communication systems; low density parity check codes; post PAR simulation; power consumption; turbo encoders; Decoding; Hardware; Parity check codes; Systematics; Turbo codes; Convolution Codes; Error Correction Codes (ECC); Low Density Parity Check (LDPC); Parity Check Matrices; Recursive Systematic Convolution (RSC); Run Length Coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information and Communication Technologies (ICICT), 2011 International Conference on
Conference_Location :
Karachi
Print_ISBN :
978-1-4577-1553-2
Type :
conf
DOI :
10.1109/ICICT.2011.5983574
Filename :
5983574
Link To Document :
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