DocumentCode :
2752501
Title :
Test sequence compaction for sequential circuits with reset states
Author :
Higami, Yoshinobu ; Takamatsu, Yuzo ; Kinoshita, Kozo
Author_Institution :
Ehime Univ., Matsuyama, Japan
fYear :
2000
fDate :
2000
Firstpage :
165
Lastpage :
170
Abstract :
Proposes a static test compaction method for sequential circuits with reset states under a single stuck-at fault assumption. The proposed method first finds unremovable vectors by fault-dropping fault simulation or by non-fault-dropping fault simulation. Next, a subset of test vectors other than unremovable vectors are replaced with a reset signal. Detection of faults detected by an original test sequence is guaranteed by logic simulation and fault simulation for test subsequences. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method
Keywords :
automatic test pattern generation; fault simulation; logic simulation; logic testing; sequential circuits; signal detection; vectors; benchmark circuits; fault detection; fault-dropping fault simulation; logic simulation; nonfault-dropping fault simulation; reset signal; reset states; sequential circuits; single stuck-at fault assumption; test compaction method; test sequence compaction; test subsequences; test vectors; unremovable vectors; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Compaction; Electrical fault detection; Fault detection; Logic testing; Sequential analysis; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
ISSN :
1081-7735
Print_ISBN :
0-7695-0887-1
Type :
conf
DOI :
10.1109/ATS.2000.893620
Filename :
893620
Link To Document :
بازگشت