DocumentCode
2753333
Title
Analysis of Resistive Bridging Defects in a Synchronizer
Author
Kim, Hyoung-Kook ; Jone, Wen-Ben ; Wang, Laung-Terng ; Wu, Shianling
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Cincinnati, Cincinnati, OH, USA
fYear
2009
fDate
23-26 Nov. 2009
Firstpage
443
Lastpage
449
Abstract
This paper presents fault modeling and analysis for resistive bridging defects in a synchronizer constructed with two D flip-flops. Bridging defects are exhaustively injected into any two nodes of the synchronizer to find all possible faults that might occur in the synchronizer, and HSPICE is used to perform circuit analysis.
Keywords
fault simulation; flip-flops; synchronisation; D flip-flops; HSPICE; circuit analysis; fault modeling; resistive bridging defects; synchronizer; Circuit faults; Circuit testing; Clocks; Flip-flops; Frequency synchronization; Inverters; Metastasis; Predictive models; Timing; Voltage; fault analysis; fault modeling; resistive bridging defect; synchronizer;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2009. ATS '09.
Conference_Location
Taichung
ISSN
1081-7735
Print_ISBN
978-0-7695-3864-8
Type
conf
DOI
10.1109/ATS.2009.13
Filename
5359283
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