DocumentCode :
275339
Title :
The VHDL validation suite
Author :
Armstrong, James ; Cho, Chang ; Shah, Sandeep ; Kosaraju, Chakravarthy
Author_Institution :
Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
fYear :
1990
fDate :
24-28 Jun 1990
Firstpage :
2
Lastpage :
7
Abstract :
A validation suite for the IEEE standard VHSIC Hardware Description Language (VHDL) is discussed along with its executive manager. Test points are generated from the VHDL LRM (language reference manual) syntax diagrams and sentences. Each test in the suite contains a test header which is specially formatted and keeps information such as test point, test objective, test result, and test type. The suit executive manager is menu-driven and efficiently classifies the tests based on different criterion defined in the test header. Coverage is defined to measure how closely a VHDL tool covers the LRM and is also computed by the suite executive manager
Keywords :
VLSI; logic testing; program testing; specification languages; IEEE standard VHSIC Hardware Description Language; VHDL LRM syntax diagrams; VHDL tool; VHDL validation suite; language reference manual; menu-driven; suite executive manager; test header; test objective; test point; test result; test type; Application software; Engineering management; Measurement standards; NIST; Silicon compiler; Software measurement; Software standards; Software testing; Software tools; Standards development;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location :
Orlando, FL
ISSN :
0738-100X
Print_ISBN :
0-89791-363-9
Type :
conf
DOI :
10.1109/DAC.1990.114819
Filename :
114819
Link To Document :
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