DocumentCode :
275351
Title :
Timing analysis in precharge/unate networks
Author :
McGeer, Patrick C. ; Brayton, Robert K.
Author_Institution :
Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
fYear :
1990
fDate :
24-28 Jun 1990
Firstpage :
124
Lastpage :
129
Abstract :
The false path problem on precharge/unate networks, more commonly known as dynamic CMOS networks, is considered. It is demonstrated that the tight criterion of dynamic sensitization is robust on such networks, though it has been shown to be nonrobust on general networks. Tighter bounds may be obtained on the length of the critical path in precharge/unate networks than in general static networks. A dynamic programming procedure to find the longest dynamically sensitizable path in a precharge/unate network is derived
Keywords :
CMOS integrated circuits; circuit analysis computing; dynamic programming; logic CAD; logic testing; critical path; dynamic CMOS networks; dynamic programming; dynamic sensitization; false path problem; longest dynamically sensitizable path; precharge network; precharge/unate network; Circuit analysis; Dynamic programming; Information analysis; Intelligent networks; Logic functions; Logic programming; Propagation delay; Robustness; Timing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location :
Orlando, FL
ISSN :
0738-100X
Print_ISBN :
0-89791-363-9
Type :
conf
DOI :
10.1109/DAC.1990.114841
Filename :
114841
Link To Document :
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