Corolla based circuit partitioning and resynthesis

Author

Dey, Sujit ; Brglez, Franc ; Kedem, Gershon

Author_Institution

Dept. of Comput. Sci., Duke Univ., Durham, NC, USA

fYear

1990

fDate

24-28 Jun 1990

Firstpage

607

Lastpage

612

Abstract

Application of corolla-based partitioning to improve synthesis of large multi-level logic circuits is introduced. First, stem regions, petals, and corollas are defined. Next, the partitioning algorithm is outlined and the resynthesis process is described. Results of partitioning and logic resynthesis on a variety of large circuit benchmarks are summarized. It is found that logic resynthesis based on corolla partitioning consistently reduces reconvergent fanout branches, transistor pairs and layout areas, while improving circuit delay and testability

Keywords

circuit CAD; logic CAD; circuit delay; circuit partitioning; corolla partitioning; corolla-based partitioning; layout areas; logic CAD; logic resynthesis; multi-level logic circuits; partitioning algorithm; petals; reconvergent fanout branches; resynthesis process; stem regions; testability; transistor pairs; Automatic testing; Benchmark testing; Boolean functions; Circuit synthesis; Circuit testing; Delay; Logic circuits; Network synthesis; Partitioning algorithms; Signal analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Conference_Location

Orlando, FL

ISSN

0738-100X

Print_ISBN

0-89791-363-9

Type

conf

DOI

10.1109/DAC.1990.114926

Filename

114926