Title :
Techniques to reduce power in fast wide memories [CMOS SRAMs]
Author :
Amrutur, B.S. ; Horowitz, M.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
Memories contain large arrays with high capacitance bitlines and IO lines. To reduce the power of memory accesses we limit the swings on these by controlling the time the lines are driven by using a replica feedback. The swings are set to 10% of the supply over a wide range of process and operating conditions.
Keywords :
SRAM chips; CMOS; IO lines; SRAMs; bitlines; capacitance; fast wide memories; memory accesses; operating conditions; process conditions; replica feedback; CMOS technology; Capacitance; Circuit simulation; Circuit testing; Delay; Feedback; Pulse amplifiers; Random access memory; Space vector pulse width modulation; Voltage;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573217
