DocumentCode :
2755192
Title :
The case for partial scan
Author :
Rearick, Jeff
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
fYear :
1997
fDate :
1-6 Nov 1997
Firstpage :
1032
Abstract :
The full scan design methodology undisputably has many benefits throughout the process of ASIC and system design and during the life cycle of a product that may justify its use, but it has some very definite costs as well. These include larger die area, reduced circuit performance and the fact that there are usually a number of memory elements which are not scanned. It is suggested that partial scan be useful in augmenting the test coverage on critical portions of high performance chips, and that it can also serve as the basis for an area-efficient design methodology on any chip. Partial scan is another facet of the continual improvement process in IC design. As new developments in flip-flop selection and sequential ATPG are integrated into design flows, partial scan can become as push-button as full scan now is. When coupled with a design methodology driven by timing analysis and synthesis, partial scan could well be the key to producing designs that are optimized for performance, area, and testability
Keywords :
application specific integrated circuits; automatic testing; economics; integrated circuit testing; ASIC; IC testing; costs; die area; flip-flop; life cycle; partial scan; sequential ATPG; test coverage; testability; timing analysis; Application specific integrated circuits; Automatic test pattern generation; Circuit optimization; Circuit testing; Costs; Design methodology; Flip-flops; Performance analysis; Process design; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-4209-7
Type :
conf
DOI :
10.1109/TEST.1997.639722
Filename :
639722
Link To Document :
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