Yield Ramp up by Scan Chain Diagnosis

Advances in the semiconductor manufacturing technologies have resulted in the defect distribution to both random defects and process weakness due to smaller geometry. The ever-increasing complexity of the designs makes the traditional failure analysis and yield learning techniques inadequate for finding the root cause. In early stage of new technologies and new devices, yield at wafer sort is most likely to be low. Failure analysis for the majority defects during manufacturing wafer test is a good means to ramp up yield quickly to have more focus on solving the most severe process weakness. To achieve this goal, we rely on both logic diagnosis flow and scan chain diagnosis flow to extend our PFA sample size to make better judgment on the majority failure. Experience shows that using scan chain diagnosis has some advantages that are described in the paper.