• DocumentCode
    275652
  • Title

    Parallel architecture for VLSI implementation of a 2-dimensional discrete cosine transform for image coding

  • Author

    Liebsch, W.

  • Author_Institution
    Heinrich-Hertz-Inst. Berlin GmbH, West Germany
  • fYear
    1989
  • fDate
    18-20 Jul 1989
  • Firstpage
    609
  • Lastpage
    612
  • Abstract
    A new efficient parallel architecture is presented for high-speed two-dimensional discrete cosine transform (DCT) for image data compression with a block size of 8×8 picture elements. This circuit is applicable in advanced television and HDTV systems working at video sampling-rate up to 80 MHz and can be realized in CMOS technology as a single VLSI component
  • Keywords
    CMOS integrated circuits; VLSI; codecs; computerised picture processing; digital signal processing chips; parallel architectures; 2-dimensional discrete cosine transform; 80 MHz; CMOS technology; DSP; HDTV; VLSI; advanced television; codecs; image coding; image data compression; image processing chip; parallel architecture;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Image Processing and its Applications, 1989., Third International Conference on
  • Conference_Location
    Warwick
  • Type

    conf

  • Filename
    132201
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=275652